とりあえず Unimon までは OK、っと。こちらは asano さんに感謝。78K/3 は何にもないのでこれからです。
diff -aruN ../unimon/unimon-20241231/tlcs90/config/config.inc tlcs90/config/config.inc --- ../unimon/unimon-20241231/tlcs90/config/config.inc 2020-11-29 16:55:53.000000000 +0900 +++ tlcs90/config/config.inc 2025-01-31 22:50:13.000000000 +0900 @@ -9,8 +9,8 @@ ENTRY: EQU 0080H ; Entry point -WORK_B: equ 0EF00H -STACK: equ 0EFEFH +WORK_B: equ 0BF00H +STACK: equ 0BFFFH BUFLEN: equ 16 @@ -23,24 +23,26 @@ USE_REGCMD = 1 ; R(egister) command and related functions ;; Port 4 Control Register -P4CR_V: EQU 0FH ; Port 4 : Output A16-A19 +P4CR_V: EQU 01H ; Port 4 : Output A16 only. + ; bit 1..3 : output port ;;; ;;; Toshiba TLCS-90 internal ;;; USE_DEV_TLCS90 = 1 - IF USE_DEV_TLCS90 - - ;; Serial Channel Mode Register -SCMOD_V:EQU 3BH ; 8bit, BRG/2 - - ;; Timer/Serial Channel Operation Control Register -TRUN_V: EQU 0E0H ; 19200/9600bps - - ;; Port 3 Control Register -P3CR_V: EQU 4AH ; Normal wait, TxD,RxD +USE_DEV_TLCS90SBC = 1 + IF USE_DEV_TLCS90 +;P4CR_V: EQU 01H +P4_V: EQU 00H +TREG2_V:EQU 05H ; Timer 2 Value = 19200bps x 16 x 8 x 5 = 12.288MHz +TMOD_V: EQU 00H ; All 8bit timer +TCLK_V: EQU 55H ; ALL counter sources are PHIT1 +TRUN_V: EQU 24H ; Timer2 count, all other timers are disabled +SCMOD_V:EQU 38H ; 8bit, To2TRG +SCCR_V: EQU 00H ; noparity, CTS disable +P3CR_V: EQU 46H ; Normal wait, TxD,RxD ENDIF ;;; diff -aruN ../unimon/unimon-20241231/tlcs90/dev/dev_tlcs90.asm tlcs90/dev/dev_tlcs90.asm --- ../unimon/unimon-20241231/tlcs90/dev/dev_tlcs90.asm 2019-09-25 13:34:47.000000000 +0900 +++ tlcs90/dev/dev_tlcs90.asm 2025-01-19 16:51:49.000000000 +0900 @@ -4,18 +4,43 @@ INIT: + IF USE_DEV_TLCS90SBC + ;; Reset PORTS + XOR A,A + LD (P4),A + LD (BXADR),A + LD (BYADR),A + LD (P4CR),P4CR_V + + ;; TIMER2 setup + LD (TMOD),TMOD_V + LD (TREG2),TREG2_V + LD (TCLK),TCLK_V + LD (TRUN),TRUN_V + + NOP + NOP + NOP + ;; Reset USART + LD (SCMOD),SCMOD_V + LD (SCCR),SCCR_V + LD (TRUN),TRUN_V + LD (P3CR),P3CR_V + + ELSEIF LD A,SCMOD_V LD (SCMOD),A LD A,TRUN_V LD (TRUN),A LD A,P3CR_V LD (P3CR),A - + ENDIF + ;; Write dummy (to set IRFTX) XOR A,A LD (SCBUF),A - + RET CONIN: diff -aruN ../unimon/unimon-20241231/tlcs90/tlcs90.inc tlcs90/tlcs90.inc --- ../unimon/unimon-20241231/tlcs90/tlcs90.inc 2020-11-29 16:55:53.000000000 +0900 +++ tlcs90/tlcs90.inc 2025-01-19 16:45:05.000000000 +0900 @@ -5,12 +5,22 @@ IRFH: EQU 0FFC3H ; Interrupt Request Flip-Flop P3CR: EQU 0FFC7H ; Port 3 Control Register +P4: EQU 0FFC8H ; Port 4 Data Register P4CR: EQU 0FFC9H ; Port 4 Control Register +BX: EQU 0FFECH ; BX register +BY: EQU 0FFECH ; BY register WDMOD: EQU 0FFD2H ; Watchdog Timer Mode Register WDCR: EQU 0FFD3H ; Watchdog Timer Control Register SCMOD: EQU 0FFE9H ; Serial Channel Mode Register SCCR: EQU 0FFEAH ; Serial Channel Control Register SCBUF: EQU 0FFEBH ; Serial Transmission/Receiving Buffer Register -BX: EQU 0FFECH ; Bank Register BX -BY: EQU 0FFEDH ; Bank Register BY +BXADR: EQU 0FFECH ; Bank Register BX +BYADR: EQU 0FFEDH ; Bank Register BY +TREG0: EQU 0FFD4H ; Timer Data Register 0 +TREG1: EQU 0FFD5H ; Timer Data Register 1 +TREG2: EQU 0FFD6H ; Timer Data Register 2 +TREG3: EQU 0FFD7H ; Timer Data Register 3 +TCLK: EQU 0FFD8H ; Timer Clock Control Register +TFFCR: EQU 0FFD9H ; Timer/Serial Channel Operation Control Register +TMOD: EQU 0FFDAH ; Timer/Serial Channel Operation Control Register TRUN: EQU 0FFDBH ; Timer/Serial Channel Operation Control Register diff -aruN ../unimon/unimon-20241231/tlcs90/unimon_tlcs90.asm tlcs90/unimon_tlcs90.asm --- ../unimon/unimon-20241231/tlcs90/unimon_tlcs90.asm 2020-11-29 16:55:53.000000000 +0900 +++ tlcs90/unimon_tlcs90.asm 2025-01-03 17:56:56.000000000 +0900 @@ -5,7 +5,7 @@ CPU 90c141 -TARGET: equ "90C802" +TARGET: equ "90C840" INCLUDE "config.inc"
